As the amount of data transmitted between semiconductor chips and the transfer rate of the data are increased, the area and power occupied by a transmission/reception unit within the semiconductor chip continue to be increased. As research related to a semiconductor device, active research is being carried out in order to increase efficiency of circuits.
During the data transmission, an error attributable to a data loss during transmission may be minimized only when the data is transmitted at a specific time interval and a reception unit recovers the data at the same time interval. To this end, the clock signal of a specific frequency is required, and information about the clock signal of the specific frequency is transmitted from a transmission unit to the reception unit so that the data may be recovered correctly. A current data transmission method between semiconductor chips often includes a clock-forwarded signaling method and a clock-embedded signaling method. The former is a method of directly providing a clock signal for recovery to the reception unit using a separate pin for sending the clock signal in addition to a pin for data transmission, and is widely used in a method of transmitting and receiving a large amount of data between a semiconductor memory chip and a CPU which requires multiple data transmission/reception channels. This method is also known as source-synchronous signaling, meaning that synchronization is achieved by directly sending a clock signal. The latter is a method of extracting, by the reception unit, information about the transition of a transmitted differential data signal itself, recovering a clock signal in itself, and using the recovered clock for data recovery. A Clock and Data Recovery (CDR) circuit is used for such a function.
As data transmission/reception rate between semiconductor chips increases, an increase of a Bit Error Rate (BER) attributable to noise on the power lines that is present inside and outside the chips becomes an important issue. Such noise results in jitter noise by which the transition time of a data signal is changed. A symbol period indicative of the period of one bit of data is gradually reduced as the data transfer rate is increased, and the influence of jitter noise is gradually increased along with high speediness. As a result, the jitter noise functions as an important factor that limits maximum data transfer rate. If such jitter noise differently affects the data signal and the clock signal on the path along which data synchronized with the clock signal at the transmitter is transferred to the reception unit through a communication channel, a cross correlation between the data and the recovery clock signal at the end of the channel is deteriorated when the reception unit recovers the data from the clock signal, leading to an increase of the BER. In order to prevent such a BER increment, if the path along which the data is transmitted is matched with the path along which the clock signal is transmitted to the utmost so that noise influence due to the power supply lines affects the same jitter noise in the data signal and the recovery clock signal, a low BER may be maintained during recovering data at the receiver even in the presence of power noise.
In high-speed data transmission/reception between semiconductor chips, the two methods (clock-forwarded signaling and clock-embedded signaling) have advantages and disadvantages. In the former case, there often exists a difference between the transmission/reception paths of the data signal and the clock signal, and a difference of time delay on the paths attributable to parasitic capacitance and resistance components associated with a difference in the routing topology of the lines of the signals. Such a phenomenon results in a great path difference especially when recovering the data from multiple transmission/reception channels using a single clock signal. This path difference is generated when distributing the clock signal to multiple data transmission/reception circuits. Furthermore, a difference in the routing topology of a medium conductor (or a transmission channel) that connects semiconductor chips on the outside of the semiconductor chips, that is, on a PCB makes this method as a disadvantageous method in high-speed signal transmission/reception because it often causes a difference in the path between data and the clock signal.
Meanwhile, the latter case is a method that is historically used to send and receive data to and from a long distance using a transmission cable. In this method, in order to prevent great expenses from occurring in adding a transmission cable for a separate clock signal in addition to data cable to a long distance, when a transmission unit sends a differential data signal to two pins, a reception unit (or CDR in this case) recovers the clock signal from information by which a received digital data shifts from 0 to 1 or from 1 to 0 and uses the recovered clock signal for data recovery. Such a method is widely applied to semiconductor circuits as the transfer rate between semiconductor chips is recently increased. In this case, however, a CDR circuit itself is complicated, and the fast varying jitter noise of a data signal that is affected by rapidly changing power noise is not sufficiently rapidly incorporated into the clock signal due to the time delay of the CDR circuit itself. Accordingly, such a method functions as a factor to increase the BER in high-speed data transmission/reception. Furthermore, such a method is disadvantageous in that it deteriorates power efficiency because the CDR circuit needs to operate continuously while data is transmitted.